A cycle simulation tool (simulator) may be employed to test logic included in paths of an integrated circuit (IC) without considering propagation delay (e.g., introduced by wires and logic included in the path). In contrast, a timing simulator may be employed to account for timing while testing logic included in paths of the IC. However, owning and maintaining both a cycle simulator and timing simulator may be cost-prohibitive. For example, the cost of a timing simulator may prevent an owner of a cycle simulator from purchasing the timing simulator. Further, even if purchased, a large amount of time may be required to customize the timing simulator for the owner's intended application. Additionally, in some conventional systems, an array and pointers may be employed to simulate propagation delays in the system. However, maintaining the pointers may require a large amount of time and/or resources. Consequently, methods and apparatus for considering delay introduced by a logic path of an IC while testing the IC using a cycle simulator are desired.